The present invention relates to a memory testing device and, more particularly, to a memory testing device which prevents of an excessive write and an excessive erasure that accompany simultaneous testing of a plurality of flush Electrically Erasable Programmable ROMs (EEPROMs).
Memory testing equipment is usually required to test simultaneously a plurality of memories (hereinafter referred to as DUTs) through a plurality of channels. To meet this requirement, the memory testing device usually has such a construction as depicted in FIG. 1. A pattern generation part 10 generates, in synchronization with a clock CK from a timing generator 9, a test pattern TP which is composed of a sequence of each of an expected value pattern EV, a write enable signal WE, a data pattern Di (=D.sub.il to D.sub.im) of m (m.gtoreq.1) bits and an address pattern A of plural bits. A signal generation part 20 is supplied with the write enable signal WE, the data pattern Di and the address pattern A and outputs them as waveform-shaped signals each having timing specified by a timing signal TS from the timing generator 9 and a predetermined level. These output signals (identified by the same reference characters as those of the input signals WE, Di and A, respectively) are each distributed by a signal distribution part 31 to n (n=1) channels and provided to corresponding pins of DUT1, DUT2, . . . in common to them, wherein data is written into or read out from a memory cell specified by the address A. The data thus read out of the DUT in each test channel is input into a logical comparator 3C of a logical comparison part 32, wherein it is compared with the expectation pattern EV from the pattern generator 10 at the timing of a strobe signal STR from the timing generator 9. The result of the comparison is output as a pass/fail signal S, which is applied to the pattern generator 10 as well as to control the test pattern generation sequence.
When the DUT is an ordinary memory, data of a logic "1 " (H level) is written thereinto once and then read out therefrom for comparison with an expectation. In the case of the thus written logic "1 " data, data of a logic "0 " (L level) is once written into the memory cell concerned to erase the previous data and then the newly written data is read out of the cell and compared with an expectation.
When the DUT is a flush EEPROM, however, a single write operation (or erase operation) is usually insufficient for effecting a write or erase and such an operation needs to be performed several times. The required number of write/erase cycles to complete a write (or erase) of data varies from DUT to DUT. For example, in the case of testing 100 memories at the same time, a combination write-read operation (hereinafter referred to as a W-R operation) is carried out for cells of the common address A, for instance, 20 times. In this instance, specimens for which the W-R operation had been needed 1 to 9 times before the decision signal Si becomes "PASS (OK)" are regarded as defective, and hence are rejected; specimens for which the W-R operation was needed 10 to 20 times are regarded as good, and hence are accepted; and specimens for which the decision signal Si does not become "PASS" or still remains "FAIL" after the W-R operation was performed 20 times are regarded as defective. Then each logical comparator 3C is cleared to zero by a clear signal CL from the pattern generator 10 and the same test as mentioned above is made for memory cells of the next address A+1. When the decision signal Si becomes "PASS" for all the DUTs before the W-R operation is performed 20 times, however, the address is advanced by 1 (i.e., +1) at that point, followed by the test for the cells of the new address. Such an operation is carried out by controlling the test pattern generation sequence in the pattern generator 10 on the basis of the decision signal S available from the logical comparator 3C of each channel. Although data input terminals and data output terminals of the DUT are shown to be independent of each other, they are provided as common terminals in many cases.
Since the conventional memory testing equipment is designed so that the same signal is applied, under the same condition, to a plurality of DUTs that are tested concurrently, the write (or erase) operation takes place a maximum allowable number of times (in the prior art example, 20 times for an allowable range of 10 to 20 times within which DUTs are regarded as good, for example). This poses an "excessive write (or excessive erasure)" problem to a DUT for which a write (or erase) of data has been completed by, for instance, a 10-times repetition of the write (or erase) operation.
The "excessive write" or "excessive erasure"mentioned herein means that a memory cell is overcharged positive or negative by inputting thereinto the write enable signal WE and data of the logic "1" or "0" more than a required number of times. If data of the logic "1" is excessively written, then the number of write operations of "0" required to erase "1" increases accordingly.